Function report |
Source Code:arch\x86\kernel\cpu\mtrr\generic.c |
Create Date:2022-07-28 08:06:10 |
Last Modify:2022-05-18 17:45:43 | Copyright©Brick |
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Name:Doesn't attempt to pass an error out to MTRR users* because it's quite complicated in some cases and probably not* worth it because the best error handling is to ignore it.
Proto:void mtrr_wrmsr(unsigned msr, unsigned a, unsigned b)
Type:void
Parameter:
Type | Parameter | Name |
---|---|---|
unsigned | msr | |
unsigned | a | |
unsigned | b |
526 | If wrmsr with exception handling < 0 Then |
527 | pr_err("MTRR: CPU %u: Writing MSR %x to %x:%x failed\n", smp_processor_id(), msr, a, b) |
Name | Describe |
---|---|
k8_check_syscfg_dram_mod_en | BIOS is expected to clear MtrrFixDramModEn bit, see for example* "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD* Opteron Processors" (26094 Rev. 3.30 February 2006), section* "13 |
set_fixed_range | set_fixed_range - checks & updates a fixed-range MTRR if it* differs from the value it should have*@msr: MSR address of the MTTR which should be checked and updated*@changed: pointer which indicates whether the MTRR needed to be changed*@msrwords: pointer |
set_mtrr_var_ranges | Set the MSR pair relating to a var range.* Returns true if changes are made. |
prepare_set | Since we are disabling the cache don't allow any interrupts,* they would run extremely slow and would only increase the pain.* The caller must ensure that local interrupts are disabled and* are reenabled after post_set() has been called. |
post_set | |
generic_set_mtrr | generic_set_mtrr - set variable MTRR register on the local CPU.*@reg: The register to set.*@base: The base address of the region.*@size: The size of the region. If this is 0 the region is disabled.*@type: The type of the region.* Returns nothing. |
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