Function report

Linux Kernel

v5.5.9

Brick Technologies Co., Ltd

Source Code:arch\x86\kernel\cpu\intel.c Create Date:2022-07-28 07:57:20
Last Modify:2020-03-12 14:18:49 Copyright©Brick
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Name:early_init_intel

Proto:static void early_init_intel(struct cpuinfo_x86 *c)

Type:void

Parameter:

TypeParameterName
struct cpuinfo_x86 *c
195  If CPU family > 6 || CPU family == 6 && x86_model >= 0xd Then
196  If Clear @bit in a MSR @msr.* Retval:* < 0: An error was encountered.* = 0: Bit was already cleared.* > 0: Hardware accepted the MSR write. > 0 Then
198  Maximum supported CPUID level, -1=no CPUID: = CPUID functions returning a single datum
199  get_cpu_cap(c)
203  If CPU family == 0xf && x86_model >= 0x03 || CPU family == 0x6 && x86_model >= 0x0e Then set_cpu_cap(c, TSC ticks at a constant rate )
207  If CPU family >= 6 && Not cpu_has(c, IA-64 processor ) Then microcode = intel_get_microcode_revision()
211  If ( cpu_has(c, "" Speculation Control (IBRS + IBPB) ) || cpu_has(c, "" Single Thread Indirect Branch Predictors ) || cpu_has(c, Indirect Branch Restricted Speculation ) || cpu_has(c, Indirect Branch Prediction Barrier ) || cpu_has(c, Single Thread Indirect Branch Predictors )) && bad_spectre_microcode(c) Then
215  pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n")
216  setup_clear_cpu_cap(Indirect Branch Restricted Speculation )
217  setup_clear_cpu_cap(Indirect Branch Prediction Barrier )
218  setup_clear_cpu_cap(Single Thread Indirect Branch Predictors )
219  setup_clear_cpu_cap("" Speculation Control (IBRS + IBPB) )
220  setup_clear_cpu_cap("" MSR SPEC_CTRL is implemented )
221  setup_clear_cpu_cap("" Single Thread Indirect Branch Predictors )
222  setup_clear_cpu_cap(Speculative Store Bypass Disable )
223  setup_clear_cpu_cap("" Speculative Store Bypass Disable )
234  If CPU family == 6 && x86_model == 0x1c && x86_stepping <= 2 && microcode < 0x20e Then
236  pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n")
237  clear_cpu_cap(c, Page Size Extensions )
241  set_cpu_cap(c, "" sysenter in IA32 userspace )
249  If CPU family == 0xF && x86_model == 0x3 && ( x86_stepping == 0x3 || x86_stepping == 0x4 ) Then x86_phys_bits = 36
260  If x86_power & 1 << 8 Then
261  set_cpu_cap(c, TSC ticks at a constant rate )
262  set_cpu_cap(c, TSC does not stop in C states )
266  If CPU family == 6 Then
268  Case x86_model == Penwell
269  Case x86_model == Cloverview
270  Case x86_model == Merriefield
271  Case x86_model == Lightning Mountain
272  set_cpu_cap(c, TSC doesn't stop in S3 state )
273  Break
274  Default
275  Break
289  If CPU family == 6 && x86_model < 15 Then clear_cpu_cap(c, Page Attribute Table )
296  If CPU family > 6 || CPU family == 6 && x86_model >= 0xd Then
297  rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable)
298  If Not (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) Then
299  pr_info("Disabled fast string operations\n")
300  setup_clear_cpu_cap(REP microcode works well )
301  setup_clear_cpu_cap(Enhanced REP MOVSB/STOSB instructions )
315  If CPU family == 5 && x86_model == 9 Then
316  pr_info("Disabling PGE capability bit\n")
317  setup_clear_cpu_cap(Page Global Enable )
320  If Maximum supported CPUID level, -1=no CPUID: >= 0x00000001 Then
323  cpuid(0x00000001, & eax, & ebx, & ecx, & edx)
329  If edx & 1U << 28 Then CPUID returned core id bits: = get_count_order((ebx >> 16) & 0xff)
333  check_mpx_erratum(c)
334  Processors which have self-snooping capability can handle conflicting* memory type across CPUs by snooping its own cache. However, there exists* CPU models in which having conflicting memory types still leads to
340  If detect_extended_topology_early(c) < 0 Then detect_ht_early(c)
Caller
NameDescribe
init_intel