函数逻辑报告

Linux Kernel

v5.5.9

Brick Technologies Co., Ltd

Source Code:arch\x86\kernel\cpu\intel.c Create Date:2022-07-27 08:57:42
Last Modify:2020-03-12 14:18:49 Copyright©Brick
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函数名称：early_init_intel

函数原型：static void early_init_intel(struct cpuinfo_x86 *c)

返回类型：void

参数：

类型参数名称
struct cpuinfo_x86 *c
195  如果CPU family 大于6或CPU family 恒等于6且x86_model大于等于0xd则
196  如果Clear @bit in a MSR @msr.* Retval:* < 0: An error was encountered.* = 0: Bit was already cleared.* > 0: Hardware accepted the MSR write.大于0则
198  Maximum supported CPUID level, -1=no CPUID: 等于CPUID functions returning a single datum
199  get_cpu_cap(c)
203  如果CPU family 恒等于0xf且x86_model大于等于0x03或CPU family 恒等于0x6且x86_model大于等于0x0e则set_cpu_cap(c, TSC ticks at a constant rate )
207  如果CPU family 大于等于6且非cpu_has(c, IA-64 processor )则microcode等于intel_get_microcode_revision()
211  如果cpu_has(c, "" Speculation Control (IBRS + IBPB) )或cpu_has(c, "" Single Thread Indirect Branch Predictors )或cpu_has(c, Indirect Branch Restricted Speculation )或cpu_has(c, Indirect Branch Prediction Barrier )或cpu_has(c, Single Thread Indirect Branch Predictors )的值且bad_spectre_microcode(c)则
215  打印警告信息("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n")
216  setup_clear_cpu_cap(Indirect Branch Restricted Speculation )
217  setup_clear_cpu_cap(Indirect Branch Prediction Barrier )
218  setup_clear_cpu_cap(Single Thread Indirect Branch Predictors )
219  setup_clear_cpu_cap("" Speculation Control (IBRS + IBPB) )
220  setup_clear_cpu_cap("" MSR SPEC_CTRL is implemented )
221  setup_clear_cpu_cap("" Single Thread Indirect Branch Predictors )
222  setup_clear_cpu_cap(Speculative Store Bypass Disable )
223  setup_clear_cpu_cap("" Speculative Store Bypass Disable )
234  如果CPU family 恒等于6且x86_model恒等于0x1c且x86_stepping小于等于2且microcode小于0x20e则
236  打印警告信息("Atom PSE erratum detected, BIOS microcode update recommended\n")
237  clear_cpu_cap(c, Page Size Extensions )
241  set_cpu_cap(c, "" sysenter in IA32 userspace )
249  如果CPU family 恒等于0xF且x86_model恒等于0x3且x86_stepping恒等于0x3或x86_stepping恒等于0x4的值则x86_phys_bits等于36
260  如果x86_power按位与1左移8位则
261  set_cpu_cap(c, TSC ticks at a constant rate )
262  set_cpu_cap(c, TSC does not stop in C states )
266  如果CPU family 恒等于6则
268  当:x86_model恒等于Penwell
269  当:x86_model恒等于Cloverview
270  当:x86_model恒等于Merriefield
271  当:x86_model恒等于Lightning Mountain
272  set_cpu_cap(c, TSC doesn't stop in S3 state )
273  退出
274  默认
275  退出
289  如果CPU family 恒等于6且x86_model小于15则clear_cpu_cap(c, Page Attribute Table )
296  如果CPU family 大于6或CPU family 恒等于6且x86_model大于等于0xd则
297  rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable)
298  如果非misc_enable按位与MSR_IA32_MISC_ENABLE_FAST_STRING的值则
299  打印信息("Disabled fast string operations\n")
300  setup_clear_cpu_cap(REP microcode works well )
301  setup_clear_cpu_cap(Enhanced REP MOVSB/STOSB instructions )
315  如果CPU family 恒等于5且x86_model恒等于9则
316  打印信息("Disabling PGE capability bit\n")
317  setup_clear_cpu_cap(Page Global Enable )
320  如果Maximum supported CPUID level, -1=no CPUID: 大于等于0x00000001则
323  cpuid(0x00000001, & eax, & ebx, & ecx, & edx)
329  如果edx按位与1U左移28位则CPUID returned core id bits: 等于get_count_order((ebx >> 16) & 0xff)
333  check_mpx_erratum(c)
334  Processors which have self-snooping capability can handle conflicting* memory type across CPUs by snooping its own cache. However, there exists* CPU models in which having conflicting memory types still leads to
340  如果detect_extended_topology_early(c)小于0则detect_ht_early(c)
调用者
名称描述
init_intel