函数逻辑报告 |
Source Code:include\linux\irq.h |
Create Date:2022-07-27 08:32:18 |
Last Modify:2020-03-12 14:18:49 | Copyright©Brick |
首页 | 函数Tree |
注解内核,赢得工具 | 下载SCCT | English |
函数名称:irq_reg_writel
函数原型:static inline void irq_reg_writel(struct irq_chip_generic *gc, unsigned int val, int reg_offset)
返回类型:void
参数:
类型 | 参数 | 名称 |
---|---|---|
struct irq_chip_generic * | gc | |
unsigned int | val | |
int | reg_offset |
1169 | 如果reg_writel则reg_writel(val, reg_base + reg_offset) |
1171 | 否则writel(val, reg_base + reg_offset) |
名称 | 描述 |
---|---|
irq_gc_mask_disable_reg | q_gc_mask_disable_reg - Mask chip via disable register*@d: irq_data* Chip has separate enable/disable registers instead of a single mask* register. |
irq_gc_mask_set_bit | q_gc_mask_set_bit - Mask chip via setting bit in mask register*@d: irq_data* Chip has a single mask register. Values of this register are cached* and protected by gc->lock |
irq_gc_mask_clr_bit | q_gc_mask_clr_bit - Mask chip via clearing bit in mask register*@d: irq_data* Chip has a single mask register. Values of this register are cached* and protected by gc->lock |
irq_gc_unmask_enable_reg | q_gc_unmask_enable_reg - Unmask chip via enable register*@d: irq_data* Chip has separate enable/disable registers instead of a single mask* register. |
irq_gc_ack_set_bit | q_gc_ack_set_bit - Ack pending interrupt via setting bit*@d: irq_data |
irq_gc_ack_clr_bit | q_gc_ack_clr_bit - Ack pending interrupt via clearing bit*@d: irq_data |
irq_gc_mask_disable_and_ack_set | q_gc_mask_disable_and_ack_set - Mask and ack pending interrupt*@d: irq_data* This generic implementation of the irq_mask_ack method is for chips* with separate enable/disable registers instead of a single mask* register and where a pending interrupt is |
irq_gc_eoi | q_gc_eoi - EOI interrupt*@d: irq_data |
源代码转换工具 开放的插件接口 | X |
---|---|
支持:c/c++/esqlc/java Oracle/Informix/Mysql 插件可实现:逻辑报告 代码生成和批量转换代码 |