函数源码 |
Source File:arch\x86\kernel\cpu\mce\p5.c |
Create Date:2022-07-27 09:02:39 |
首页 | Copyright©Brick |
44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 | /* Set up machine check reporting for processors with Intel style MCE: */ void intel_p5_mcheck_init( struct cpuinfo_x86 *c) { u32 l, h; /* Default P5 to off as its often misconnected: */ if (!mce_p5_enabled) return ; /* Check for MCE support: */ if (!cpu_has(c, X86_FEATURE_MCE)) return ; machine_check_vector = pentium_machine_check; /* Make sure the vector pointer is visible before we enable MCEs: */ wmb(); /* Read registers before enabling: */ rdmsr(MSR_IA32_P5_MC_ADDR, l, h); rdmsr(MSR_IA32_P5_MC_TYPE, l, h); pr_info( "Intel old style machine check architecture supported.\n" ); /* Enable MCE: */ cr4_set_bits(X86_CR4_MCE); pr_info( "Intel old style machine check reporting enabled on CPU#%d.\n" , smp_processor_id()); } |