Function report |
Source Code:arch\x86\kernel\cpu\mce\intel.c |
Create Date:2022-07-28 08:02:33 |
Last Modify:2020-03-12 14:18:49 | Copyright©Brick |
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Name:Enable CMCI (Corrected Machine Check Interrupt) for available MCE banks* on this CPU. Use the algorithm recommended in the SDM to discover shared* banks.
Proto:static void cmci_discover(int banks)
Type:void
Parameter:
Type | Parameter | Name |
---|---|---|
int | banks |
271 | bios_wrong_thresh = 0 |
273 | raw_spin_lock_irqsave( & cmci_discover_lock protects against parallel discovery attempts* which could race against each other., flags) |
276 | bios_zero_thresh = 0 |
278 | If st_bit - Determine whether a bit is set*@nr: bit number to test*@addr: Address to start counting from Then Continue |
282 | If st_bit - Determine whether a bit is set*@nr: bit number to test*@addr: Address to start counting from Then Continue |
285 | rdmsrl(MSR_IA32_MCx_CTL2(i), val) |
288 | If val & CTL2 register defines Then |
291 | Continue |
294 | If Not bios_cmci_threshold Then |
295 | val &= ~MCI_CTL2_CMCI_THRESHOLD_MASK |
296 | val |= CMCI_THRESHOLD |
297 | Else if Not (val & MCI_CTL2_CMCI_THRESHOLD_MASK) Then |
303 | bios_zero_thresh = 1 |
304 | val |= CMCI_THRESHOLD |
307 | val |= CTL2 register defines |
308 | wrmsrl(MSR_IA32_MCx_CTL2(i), val) |
309 | rdmsrl(MSR_IA32_MCx_CTL2(i), val) |
312 | If val & CTL2 register defines Then |
321 | If bios_cmci_threshold && bios_zero_thresh && val & MCI_CTL2_CMCI_THRESHOLD_MASK Then bios_wrong_thresh = 1 |
324 | Else |
328 | raw_spin_unlock_irqrestore( & cmci_discover_lock protects against parallel discovery attempts* which could race against each other., flags) |
329 | If bios_cmci_threshold && bios_wrong_thresh Then |
330 | pr_info_once("bios_cmci_threshold: Some banks do not have valid thresholds set\n") |
332 | pr_info_once("bios_cmci_threshold: Make sure your BIOS supports this boot option\n") |
Name | Describe |
---|---|
cmci_rediscover_work_func | |
cmci_reenable | Reenable CMCI on this CPU in case a CPU down failed. |
intel_init_cmci |
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