Function report

Linux Kernel

v5.5.9

Brick Technologies Co., Ltd

Source Code:arch\x86\kernel\cpu\mce\core.c Create Date:2022-07-28 08:00:32
Last Modify:2020-03-12 14:18:49 Copyright©Brick
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Name:Poll for corrected events or events that happened before reset.* Those are just logged through /dev/mcelog.* This is executed in standard interrupt context.* Note: spec recommends to panic for fatal unsignalled* errors here

Proto:bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)

Type:bool

Parameter:

TypeParameterName
enum mcp_flagsflags
mce_banks_t *b
699  mce_banks = this_cpu_ptr(mce_banks_array)
700  bool error_seen = false
704  this_cpu_inc(mce_poll_count)
706  Collect all global (w.r.t. this processor) status about this machine* check into our "mce" struct so that we can use it later to assess* the severity of the problem as we read per-bank specific details.
708  If flags & log time stamp Then CPU time stamp counter = dtsc() - returns the current TSC without ordering constraints* rdtsc() returns the result of RDTSC as a 64-bit integer
711  When i < Operations with implied preemption/interrupt protection. These* operations can be used without worrying about preemption or interrupt.(mce_num_banks) cycle
712  If Not subevents to enable || Not st_bit - Determine whether a bit is set*@nr: bit number to test*@addr: Address to start counting from Then Continue
715  Bank's MCi_MISC MSR = 0
716  Bank's MCi_ADDR MSR = 0
717  Machine check bank reporting the error = i
719  The "volatile" is due to gcc bugs ()
720  Bank's MCi_STATUS MSR = MSR access wrappers used for error injection
723  If Not (Bank's MCi_STATUS MSR & valid error ) Then Continue
730  If flags & MCP_UC || Not (Bank's MCi_STATUS MSR & uncorrected error ) Then Go to log_it
739  If Not ser Then
740  If Bank's MCi_STATUS MSR & uncorrected error Then Continue
742  Go to log_it
746  If Not (Bank's MCi_STATUS MSR & r enabled ) Then Go to log_it
753  If Not (Bank's MCi_STATUS MSR & processor context corrupt ) && Not (Bank's MCi_STATUS MSR & Signaled machine check ) Then Go to log_it
761  Continue
763  log_it :
764  error_seen = true
766  Read ADDR and MISC registers.
768  Error severity = mce_severity( & m, tolerant, NULL, false)
774  If Not (flags & MCP_DONTLOG) && Not dont_log_ce Then mce_log( & m)
776  Else if Check if the address reported by the CPU is in a format we can parse.* It would be possible to add code for most other cases, but all would* be somewhat complicated (e.g. segment offset would require an instruction* parser) Then
782  If Not mce_gen_pool_add( & m) Then mce_schedule_work()
789  mce_wrmsrl(status(i), 0)
797  This function forces the icache and prefetched instruction stream to* catch up with reality in two very specific cases:* a) Text was modified using one virtual address and is about to be executed* from the same physical page at a different virtual address
799  Return error_seen
Caller
NameDescribe
mce_timer_fn
__mcheck_cpu_init_generic
mce_intel_cmci_poll
intel_threshold_interruptThe interrupt handler. This is called on every event.* Just call the poller directly to log any events.* This could in theory increase the threshold under high load,* but doesn't for now.
cmci_recheckJust in case we missed an event during initialization check* all the CMCI owned banks.