Function report |
Source Code:arch\x86\kernel\aperture_64.c |
Create Date:2022-07-28 08:53:14 |
| Last Modify:2020-03-17 10:38:51 | Copyright©Brick |
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| Annotation kernel can get tool activity | Download SCCT | Chinese |
Name:gart_iommu_hole_init
Proto:int __init gart_iommu_hole_init(void)
Type:int
Parameter:Nothing
| 389 | agp_aper_base = 0 , agp_aper_order = 0 |
| 390 | aper_alloc = 0 , aper_order = 0 , last_aper_order = 0 |
| 391 | last_aper_base = 0 |
| 392 | valid_agp = 0 |
| 395 | If Not amd_gart_present() Then Return -ENODEV |
| 398 | If gart_iommu_aperture_disabled || Not fix_aperture || Not early_pci_allowed() Then Return -ENODEV |
| 402 | pr_info("Checking aperture...\n") |
| 404 | If Not fallback_aper_force Then agp_aper_base = Look for an AGP bridge |
| 407 | fix = 0 |
| 408 | node = 0 |
| 419 | If Not Ignores subdevice/subvendor but as far as I can figure out* they're useless anyways Then Continue |
| 423 | gart_iommu_aperture = 1 |
| 424 | iommu_init = gart_iommu_init |
| 426 | ctl = Direct PCI access. This is used for PCI accesses in early boot beforethe PCI subsystem works. |
| 435 | ctl &= ~Aperture control register bits. |
| 436 | write_pci_config(bus, slot, 3, K8 On-cpu GART registers , ctl) |
| 438 | aper_order = ctl >> 1 & 7 |
| 439 | aper_size = 32 * 1024 * 1024 << aper_order |
| 440 | aper_base = Direct PCI access. This is used for PCI accesses in early boot beforethe PCI subsystem works. & 0x7fff |
| 441 | aper_base <<= 25 |
| 443 | pr_info("Node %d: aperture [bus addr %#010Lx-%#010Lx] (%uMB)\n", node, aper_base, aper_base + aper_size - 1, aper_size >> 20) |
| 446 | node++ |
| 448 | If Not aperture_valid(aper_base, aper_size, 64 << 20) Then |
| 449 | If valid_agp && agp_aper_base && agp_aper_base == aper_base && agp_aper_order == aper_order Then |
| 453 | If Not no_iommu && duplicated to the one in bootmem.h > 4GB broken PCI/AGP hardware bus master zone && Not printed_gart_size_msg Then |
| 456 | pr_err("you are using iommu with agp, but GART size is less than 64MB\n") |
| 457 | pr_err("please increase GART size in your BIOS setup\n") |
| 458 | pr_err("if BIOS doesn't have that option, contact your HW vendor!\n") |
| 459 | printed_gart_size_msg = 1 |
| 461 | Else |
| 467 | If last_aper_order && aper_order != last_aper_order || last_aper_base && aper_base != last_aper_base Then |
| 472 | last_aper_order = aper_order |
| 473 | last_aper_base = aper_base |
| 477 | out : |
| 478 | If Not fix && Not fallback_aper_force Then |
| 492 | If Not fallback_aper_force Then |
| 493 | aper_alloc = agp_aper_base |
| 494 | aper_order = agp_aper_order |
| 497 | If aper_alloc Then Else if Not no_iommu && duplicated to the one in bootmem.h > 4GB broken PCI/AGP hardware bus master zone || force_iommu || valid_agp || fallback_aper_force Then |
| 503 | pr_info("Your BIOS doesn't leave an aperture memory hole\n") |
| 504 | pr_info("Please enable the IOMMU option in the BIOS setup\n") |
| 505 | pr_info("This costs you %dMB of RAM\n", 32 << fallback_aper_order) |
| 509 | aper_alloc = This code runs before the PCI subsystem is initialized, so justaccess the northbridge directly. |
| 510 | If Not aper_alloc Then |
| 521 | Else |
| 522 | Return 0 |
| 541 | ctl = aper_order << 1 |
| 547 | If Not Ignores subdevice/subvendor but as far as I can figure out* they're useless anyways Then Continue |
| 550 | write_pci_config(bus, slot, 3, K8 On-cpu GART registers , ctl) |
| 551 | write_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE, aper_alloc >> 25) |
| 557 | Return 1 |
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