Function report |
Source Code:arch\x86\kernel\aperture_64.c |
Create Date:2022-07-28 08:53:08 |
| Last Modify:2020-03-17 10:38:51 | Copyright©Brick |
| home page | Tree |
| Annotation kernel can get tool activity | Download SCCT | Chinese |
Name:With kexec/kdump, if the first kernel doesn't shut down the GART and the* second kernel allocates a different GART region, there might be two* overlapping GART regions present:* - the first still used by the GART initialized in the first kernel.
Proto:void __init early_gart_iommu_check(void)
Type:void
Parameter:Nothing
| 292 | agp_aper_order = 0 |
| 293 | valid_agp = 0 |
| 295 | aper_size = 0 , aper_order = 0 , last_aper_order = 0 |
| 296 | aper_base = 0 , last_aper_base = 0 |
| 297 | aper_enabled = 0 , last_aper_enabled = 0 , last_valid = 0 |
| 299 | If Not amd_gart_present() Then Return |
| 302 | If Not early_pci_allowed() Then Return |
| 308 | fix = 0 |
| 318 | If Not Ignores subdevice/subvendor but as far as I can figure out* they're useless anyways Then Continue |
| 321 | ctl = Direct PCI access. This is used for PCI accesses in early boot beforethe PCI subsystem works. |
| 323 | aper_order = ctl >> 1 & 7 |
| 324 | aper_size = 32 * 1024 * 1024 << aper_order |
| 325 | aper_base = Direct PCI access. This is used for PCI accesses in early boot beforethe PCI subsystem works. & 0x7fff |
| 326 | aper_base <<= 25 |
| 328 | If last_valid Then |
| 329 | If aper_order != last_aper_order || aper_base != last_aper_base || aper_enabled != last_aper_enabled Then |
| 332 | fix = 1 |
| 333 | Break |
| 337 | last_aper_order = aper_order |
| 338 | last_aper_base = aper_base |
| 340 | last_valid = 1 |
| 344 | If Not fix && Not aper_enabled Then Return |
| 350 | If gart_fix_e820 && Not fix && aper_enabled Then |
| 351 | If e820__mapped_any(aper_base, aper_base + aper_size, E820_TYPE_RAM) Then |
| 357 | e820__update_table_print() |
| 361 | If valid_agp Then Return |
| 374 | If Not Ignores subdevice/subvendor but as far as I can figure out* they're useless anyways Then Continue |
| 377 | ctl = Direct PCI access. This is used for PCI accesses in early boot beforethe PCI subsystem works. |
| 378 | ctl &= ~Aperture control register bits. |
| 379 | write_pci_config(bus, slot, 3, K8 On-cpu GART registers , ctl) |
| Source code conversion tool public plug-in interface | X |
|---|---|
| Support c/c++/esqlc/java Oracle/Informix/Mysql Plug-in can realize: logical Report Code generation and batch code conversion |