函数源码 |
Source File:arch\x86\include\asm\virtext.h |
Create Date:2022-07-27 09:18:12 |
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210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 | #define SVM_CPUID_FUNC 0x8000000a#define SVM_VM_CR_SVM_DISABLE 4#define SVM_SELECTOR_S_SHIFT 4#define SVM_SELECTOR_DPL_SHIFT 5#define SVM_SELECTOR_P_SHIFT 7#define SVM_SELECTOR_AVL_SHIFT 8#define SVM_SELECTOR_L_SHIFT 9#define SVM_SELECTOR_DB_SHIFT 10#define SVM_SELECTOR_G_SHIFT 11#define SVM_SELECTOR_TYPE_MASK (0xf)#define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)#define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)#define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)#define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)#define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)#define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)#define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)#define SVM_SELECTOR_WRITE_MASK (1 << 1)#define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK#define SVM_SELECTOR_CODE_MASK (1 << 3)#define INTERCEPT_CR0_READ 0#define INTERCEPT_CR3_READ 3#define INTERCEPT_CR4_READ 4#define INTERCEPT_CR8_READ 8#define INTERCEPT_CR0_WRITE (16 + 0)#define INTERCEPT_CR3_WRITE (16 + 3)#define INTERCEPT_CR4_WRITE (16 + 4)#define INTERCEPT_CR8_WRITE (16 + 8)#define INTERCEPT_DR0_READ 0#define INTERCEPT_DR1_READ 1#define INTERCEPT_DR2_READ 2#define INTERCEPT_DR3_READ 3#define INTERCEPT_DR4_READ 4#define INTERCEPT_DR5_READ 5#define INTERCEPT_DR6_READ 6#define INTERCEPT_DR7_READ 7#define INTERCEPT_DR0_WRITE (16 + 0)#define INTERCEPT_DR1_WRITE (16 + 1)#define INTERCEPT_DR2_WRITE (16 + 2)#define INTERCEPT_DR3_WRITE (16 + 3)#define INTERCEPT_DR4_WRITE (16 + 4)#define INTERCEPT_DR5_WRITE (16 + 5)#define INTERCEPT_DR6_WRITE (16 + 6)#define INTERCEPT_DR7_WRITE (16 + 7)#define SVM_EVTINJ_VEC_MASK 0xff#define SVM_EVTINJ_TYPE_SHIFT 8#define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)#define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)#define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)#define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)#define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)#define SVM_EVTINJ_VALID (1 << 31)#define SVM_EVTINJ_VALID_ERR (1 << 11)#define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK#define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK#define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR#define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI#define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT#define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT#define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID#define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR#define SVM_EXITINFOSHIFT_TS_REASON_IRET 36#define SVM_EXITINFOSHIFT_TS_REASON_JMP 38#define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44#define SVM_EXITINFO_REG_MASK 0x0F#define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)#endif#include <asm/tlbflush.h>/* * VMX functions: */static inline int cpu_has_vmx(void){ unsigned long ecx = cpuid_ecx(1); return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */} |