函数逻辑报告

Linux Kernel

v5.5.9

Brick Technologies Co., Ltd

Source Code:arch\x86\include\asm\msr.h Create Date:2022-07-27 06:38:57
Last Modify:2020-03-12 14:18:49 Copyright©Brick
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函数名称:wrmsrl

函数原型:static inline void wrmsrl(unsigned int msr, u64 val)

返回类型:void

参数:

类型参数名称
unsigned intmsr
u64val
283  Can be uninlined because referenced by paravirt
调用者
名称描述
set_cpuid_faulting
amd_set_core_ssb_state
amd_set_ssb_virt_state
__speculation_ctrl_updateUpdate the MSRs managing speculation control, during context switch.
__switch_to_xtra
detect_null_seg_behavior
syscall_initMay not be marked __init: used by software suspend
cpu_initpu_init() initializes state that is per-CPU. Some data is already* initialized (naturally) in the bootstrap process, such as the GDT* and IDT. We reload them nevertheless, this function acts as a* 'CPU state barrier', nothing should get across.
x86_virt_spec_ctrl
x86_amd_ssb_disable
spectre_v2_select_mitigation
update_stibp_msr
__ssb_select_mitigation
x86_spec_ctrl_setup_ap
init_intel_misc_features
tsx_disable
tsx_enable
intel_epb_restore
mce_wrmsrl
__mcheck_cpu_init_clear_banks
mce_disable_error_reportingDisable machine checks on suspend and shutdown. We can't really handle* them later.
mce_reenable_cpu
cmci_toggle_interrupt_mode
cmci_discoverEnable CMCI (Corrected Machine Check Interrupt) for available MCE banks* on this CPU. Use the algorithm recommended in the SDM to discover shared* banks.
__cmci_disable_bankCaller must hold the lock on cmci_discover_lock
intel_init_lmce
intel_clear_lmce
disable_err_thresholdingTurn off thresholding banks for the following conditions:* - MC4_MISC thresholding is not supported on Family 0x15.* - Prevent possible spurious interrupts from the IF bank on Family 0x17* Models 0x10-0x2F due to Erratum #1114.
_log_error_bankReturns true if the logged error is deferred. False, otherwise.
log_error_deferredWe have three scenarios for checking for Deferred errors:* 1) Non-SMCA systems check MCA_STATUS and log error if found
clear_therm_status_log
apply_microcode_intel
mba_wrmsr_amd
mba_wrmsr_intel
cat_wrmsr
l3_qos_cfg_update
l2_qos_cfg_update
update_mba_bwFeedback loop for MBA software controller (mba_sc)* mba_sc is a feedback loop where we periodically read MBM counters and* adjust the bandwidth percentage values via the IA32_MBA_THRTL_MSRs so* that:* current bandwdith(cur_bw) < user specified
ms_hyperv_init_platform
tsc_verify_tsc_adjust
tsc_sanitize_first_cpu
lapic_next_deadline
cs5536_warm_reset
kvm_register_steal_time
kvm_guest_cpu_init
kvm_pv_disable_apf
kvm_pv_guest_cpu_reboot
kvm_get_wallclockThe wallclock is the time of day when we booted. Since then, some time may* have elapsed since the hypervisor wrote the data. So we try to account for* that with system time
kvm_register_clock
fam10h_check_enable_mmcfg
wrmsrl_on_cpu
update_debugctlmsr
x86_fsbase_write_cpu
x86_gsbase_write_cpu_inactive
__x86_pmu_enable_event
x86_pmu_disable_event
cpu_svm_disableDisable SVM on the current CPU* You should call this only if cpu_has_svm() returned true.